2018-03-30, 16:45–18:45, Max Planck
Verilog is currently the one-and-only Hardware Description Language which has a complete free and open Toolchain from Source Code down to the FPGA-Bitstream.
There are two Hardware Description Languages currently on the market. One is VHDL, very common and popular at Universities in Europa - type-safe, difficult, eloquent and smells like ADA. The other one is Verilog - reasonable more attractive for Chip Vendors and everybody who needs fast results in a short time.
Well, Verilog already had the better simulator for decades, and than came the Yosys Tool and their FOSS Toolchain and opens small Lattice FPGAs for Open Source Projects.
In this Workshop you will learn the Basics - how to write good Verilog Code, how to deal with permanent parallelism, where to find code snippets, how to simulate and synthesize. In the end, your Verilog code goes through the Yosys Toolchain and will be running live on some iCEstick Evalboards.
VirtualBox Image: http://chipforge.in-berlin.de/boxes User:eh, PW:eh
Note: The FOSS Toolchain runs with all Linux, but very straight forward with Ubuntu and their clones (Mint etc.). Please bring in your Laptop, and if you already have, your iCE40 FPGA Board.