Verilog Design Patttern
2018-04-01, 16:30–18:00, Heisenberg 1

In the last time, Verilog becomes quite popular among Hackers - based on the hype the FOSS Yosys Toolchain kicked off for the iCE40 FPGAs.

It is a known fact, that everybody can learn faster from someone which already did the stuff more than once. While freelancing in Chip Design for two decades I like to share Design Pattern in Verilog.


Design Pattern means,
- styleguides which results in readable code,
- how to write good and fast Finite State Machines, why they are so useful,
- how to deal with clock-domain crossing and why we might need that,
- how to structure your source code design files,
- how to use Makefiles for that,
and much, much more.
All with code snippets to show and explain.

I can't be stopped, until the time slot is closed.

See also: Slides